1. Field of the Invention
The present invention relates to the field of circuit testing, and more particularly, to the testing of sequential logic circuits using a single scan chain of sequential elements clocked at different frequencies and phases.
2. Art Background
Many problems are encountered in testing logic circuits having sequential components. For a solely combinational logic circuit, testing is relatively simple. A circuit tester can easily apply all possible combinations of input states and observe the resulting output states. However, because of the temporal complications introduced by sequential components, it is very difficult to determine what inputs are necessary to place the sequential logic into a given state, and to observe the storage element contents.
FIG. 1 illustrates a commonly used model of a combined sequential/combinational logic circuit. The combinational logic circuit is represented by a block 102 having inputs and outputs connected to sequential elements (flip-flops) 104. This model recognizes that different sections of the circuitry may be running at different clock frequencies. For example, microprocessors manufactured by Intel Corporation, the Assignee of the present invention, include an internal core running two or three times as fast as a peripheral clock. Similarly, some communication chips interface between different signals running at different frequencies, requiring one part of the chip to run at a slow clock while another part runs at a faster clock.
FIG. 2 illustrates a configuration for testing the circuit of FIG. 1 using scan chain techniques. Multiplexers 202 are used to select between a normal mode and a scan mode. In normal mode, the flip-flops 104 are allowed to operate as they normally would in conjunction with the combinational logic circuit 102. In scan mode, the flip-flops 104 are divided into separate scan chains for each clock frequency. In FIG. 2, the first scan chain runs at a clock frequency CLOCK1, and the second scan chain runs at a clock frequency CLOCK2. Bit patterns are applied to scan inputs SI1 and SI2, respectively, to sequentially set the state of the scan chains. The state of the flip-flops 104 is sequentially read out through scan outputs SO1 and SO2.
Note that by using the topology of FIG. 2, it is impossible to combine sequential circuits running at different clock frequencies in a single scan chain. For example, assume that the output SO1 of the first scan chain is fed into the input SI2 of the second scan chain. Further assume that the CLOCK2 frequency is three times the CLOCK1 frequency. Thus, in one CLOCK1 clock cycle the output of the last flip-flop in the first scan chain would be clocked into the first three flip-flops of the second scan chain because the second chain is running at three times the frequency of the first scan chain. Accordingly, it would be impossible to set the chain of flip-flops running at the CLOCK2 frequency to an arbitrary state if all sequential circuitry is combined in the same scan chain.
A drawback of the separate scan chain design lies in the fact that scanning in an arbitrary state is awkward and somewhat complex. As another example, assume that the first scan chain consists of ten flip-flops while the second scan chain consists of 100 flip-flops running at twice the first clock frequency. To set the state of the second scan chain, 100 bits must be fed in at the double frequency during 100 clock cycles. In real time, the first scan chain will go through only fifty clock cycles during this time period. To insure that the desired state results in the first scan chain at the same time as the second scan chain, forty dummy bits must be loaded into the first scan chain, followed by ten actual test bits. In this complicated fashion, the scan chain is set to an arbitrary state.
Scan chains also exhibit problems due to dock phase transitions. If a flip-flop is clocked on a leading edge and its output is fed into a flip-flop clocked on a trailing edge, data will be lost as it is shifted out of the first flip-flop, as will be shown below.
Accordingly, it is desired to provide a single scan chain for controlling and observing the state of a sequential logic circuit having sequential elements running at different frequencies and phases.